FPGA Hiring 3 plus to 6 plus
ASIC VERIFICATION EXP
PD EXP HIRING
RTL EXP HIRING
share cvs raminnovationlabs@gmail.com
Hiring Urgently
RTL engineers with 3 years exp with good debug experience
share cvs raminnovationlabs@gmail.com
You have a bright career with a leading service based company in
Bangalore..
Send your updated CV if looking for change in job…
JD
for Verification req:
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronic/Computer
Engineering
• Minimum 7+ years’ experience in ASIC Design Verification , with
knowledge of Computer Architecture
• Experience in any compute architecture such as x86 or ARM domain
based SOCs/Cores.
• Any Verification methodology involving OOPs concepts C++,
OVM/UVM Methodology knowledge and experience is a plus.
• Must have excellent knowledge of design & verification
flows.
• Experience in developing complex test bench/model in Verilog,
System Verilog or C++/SystemC.
• Experience in writing test plans and test cases
• Excellent hands-on debug skills
• Strong Verilog, System Verilog, PLI/DPI interface, SystemC or
C/C++, Perl/shell script programming skills.
• Must have good communication skills and the ability and desire
to foster a team environment
JD for
RTL req:
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronic/Computer
Engineering
• Minimum 5+ years’ experience of industry experience with
knowledge of Computer Architecture
• Experience in any compute architecture such as x86 or ARM domain
based SOCs/Cores.
• Experience on RTL, Micro architecture of various complex units
is a must
- Experience with Verilog, System verilog, various lint
tools is a must. Perl/Ruby scripting languages is a plus
- Excellent hands-on debug skills
• Must have good communication skills and the ability and desire
to foster a team environment
