STA in Bangalore

Location : Bangalore

Desired Skills and Experience
Full Chip STA exposure
Work with Physical Design teams and come up with optimal timing abstraction methodologies along the Physical Implementation flow
Work with design, IP and DFT teams and develop constraints
Primetime-SI and Tempus expertise on complex lower technology node designs (28nm and lower)
Good handle on AOCV, corner definitions for multi-voltage designs, RC Balance analysis
Smartness in analyzing noise, delta delay/transition, clock divergence, OCV issues and come up with optimal fixes
Familiarity with timing closure challenges associated with DDR4/Multi-protocol SerDes/USB/GPUs etc will be a big plus
Experience - 4 to 10 years



Contact:
Uday
Mulya Technologies