Gate level Simulation is used to boost up the confidence about the implementation of a design and can help to verify a dynamic circuit behavior which cannot be verified accurately by static methods. It is a significant step of the verification process.GLS overcomes the Static Timing Analysis limitations and is increasing due to low power issues, complex timing checks at 40nm and below, design for test (DFT) insertion at the gate level, and low-power considerations. For the DFT, scan chains are inserted after the gate-level net list is created; gate-level simulation is often used to determine whether scan chains are correct.Technology libraries at 45nm and below have far more timing checks, and more complex timing checks, than older process nodes. Gate-level simulation may take up to one-third of the simulation time, and could potentially take most of the debugging time. Gate-level simulation is run after RTL code is simulated and synthesized into a gate-level net list. Gate-level simulation requires a complete reset for the design.