Transaction Level Modeling for   Multimedia applications

Micro-processors (MPUs) and digital signal processors (DSPs) in Smart phones are used to provide advanced (2.75G and 3G) modem and application processing, as well as Wi-Fi, GPS and Bluetooth functionality. Embedded software design practices currently are not especially well equipped to deal with the complexities of developing inter-processor communication (IPC) software for these heterogeneous architectures. However, virtual prototyping technology is emerging which allows the creation of a high-performance, functional software model of an embedded system that is complete and it fully depicts the hardware functionality. The complexity of today's SOC has increased many folds and in past few years new methodologies have been developed to model and design these complex chips. Virtual platforms provide increased system visibility, which enables the developer to more simply isolate and debug IPC problems. System Designers and embedded software developers are accepting that SystemC Transaction level models play a key role in different phases of SOC design cycle because of its many folds benefits like architecture models, golden reference models for functional verification, early availability to act as Virtual Prototype for image quality analysis and close loop validations.

One of the Electronic System Level (ESL) techniques is Transaction Level Modeling (TLM), which have bus transactions between functional units as atomic actions and does not care about the communication protocol. Transaction level modelling is a methodology which allows system architects and verification engineers to work at a higher level of abstraction. These models can be developed as soon as initial functional specifications of SOCs which are designed and can be helpful in many phases of design cycle like architecture models for HW/SW partitioning evaluations, reference models for functional verification and virtual prototype for developing and verifying their firmware at early stages of SOC development while hardware is under development and not fully verified.

TLM is System Design Methodology which can be used to overcome these challenges. TLM are   concerned with the micro architecture like RTL models. Rather, they correspond to the architecture level of abstraction. In this context, the term transaction refers to the exchange of a data or an event between two components of a modeled and simulated system. A data transaction can be a single word, a series of words or a complex data structure that is transferred over a bus between system components. TLM models are to describe functionality in sufficient detail for the software team to start their analysis and firmware validation much earlier than using FPGA prototype. Platform is made by integrating block (IPs) SystemC TLM model and TLM wrapper of ISS processor. Each IP is written in SystemC, or has at least a SystemC wrapper with its bit true C Model plugged inside which eases functional verification engineer’s job to verify SOC by just comparing images from TLM model and RTL.